Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged.
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to select lines. However each memory cell is not directly coupled to a column sense line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column sense line.
Memory cells in an array architecture can be programmed to a desired state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of data states. For example, a single level cell (SLC) can represent two data states, e.g., 1 or 0. Flash memory cells can also store more than two data states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multidigit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four digits can have sixteen data states including an erased state.
MLC memory stores multiple digits on each cell by using different threshold voltage (Vt) levels for each state that is stored. The difference between adjacent Vt distributions may be very small for a MLC memory device as compared to a SLC memory device. The reduced margins between adjacent Vt distributions can increase the difficulty associated with distinguishing between adjacent data states, which can lead to problems such as reduced data read and/or data retrieval reliability.
Memory cells may be coupled in series between a source line and a sense line. The memory cells may be located on the string between a select gate source transistor and a select gate drain transistor. The cells adjacent to the select gate transistors are referred to herein as edge cells. The cells between the edge cells are referred to herein as non-edge cells.
The cell current associated with an edge cell after an erase operation can be higher than the cell current associated with a non-edge cell due to factors such as slow erase effects. Memory cells affected by slow erase effects can become unreliable, e.g., an erase verify operation performed on a memory cell affected by slow erase effects could fail. Slow erase effects tend to affect edge cells more than non-edge cells because of their different coupling ratios.